The present invention relates to a process for manufacturing CMOS devices.
It is known that in recent times CMOS (Complementary Metal Oxide Semiconductor) technology is acquiring increasingly larger portions of the production of integrated circuits with respect to the competing NMOS technology. This production trend is motivated by the extremely low dissipation characteristics of CMOS circuits in static conditions, by their high switching speed, by their immunity to radiation and by their compatibility with bipolar devices.
The price to be paid to achieve these advantages consists of a greater structural complexity of CMOS devices with respect to NMOS devices and a corresponding greater complexity of their manufacturing methods. If, for example, an elementary NMOS device entails the execution of seven distinct physical layers and requires five maskings, an elementary CMOS device entails the execution of twelve layers and, with current processes, requires ten maskings. A typical process currently used for manufacturing an elementary CMOS device requires, on a substrate of a first type of conductivity, the formation of a zone of the opposite type of conductivity by means of an appropriate masking step, the definition of the active areas by means of an appropriate mask, the implantation and the diffusion of appropriate ions for the definition of the insulation regions at the junction region of two regions having opposite conductivities, and field oxidation, for the obtainment of an intermediate structure, as schematically shown in FIG. 1. As can be seen, said structure comprises a substrate 1 which defines an active region, in which a transistor with a certain type of channel is to be manufactured, and a zone 2 with opposite conductivity in which the complementary transistor is to be manufactured. The structure illustrated in FIG. 1 furthermore already comprises insulation regions 3 and 4, doped so as to have opposite conductivity, and insulating field-oxide regions 5.
Subsequently, starting from this structure, a gate oxidation step is effected, leading to the formation of a thin oxide layer, followed by a step of deposition of a polycrystalline silicon layer and the doping thereof by phosphorus deposition. At this point an appropriate masking step is performed to define, in this polysilicon layer, the pattern of the gate electrodes of the transistors, obtaining a second intermediate structure, schematically shown in FIG. 2 and having, besides the previously indicated regions, the gate electrodes 6 and 7 of the two complementary transistors and the related gate insulations 6' and 7' thereof.
Two successive masking operations, performed in sequence, allow implantation, respectively in the initial substrate and in the zone with opposite type of conductivity, of the ions which are to form the source and drain electrodes of the two types of transistors and the substrate biasing regions. These two steps are schematically illustrated in FIGS. 3 and 4, wherein the reference numeral 8 indicates the first mask, for the implantation of ions which leads to the formation of the source and drain regions 9 of the transistor in the substrate and of the insulation region 9' in the zone, and 11 indicates the resist mask which allows the implantation of the opposite-type ions which lead to the formation of the source and drain regions 10 of the transistor formed in the zone and of the biasing region 10' in the substrate.
It is convenient, at this point, to explicitly point out that these ions do not penetrate below the gate electrodes. In other words, the latter screens against the implantation of the ions which are to constitute the source and drain electrodes of the transistors, which are therefore "self-aligned" with the gate regions. On the other hand, the masking layer is external to the previously defined active regions delimited by the field oxide (regions 5). This field oxide, due to its thickness, prevents the passage of the ions which are implanted. The source and the drain, therefore, are also "self-aligned" with the edge of the field oxide.
Once the diffusion of the source and drain regions has been performed in the substrate and in the opposite-type zone, the process continues with the deposition of the insulating layers, conveniently subjected to reflow by a thermal process, the opening of the contacts, the deposition of a metallic layer, the masking for the definition of the metallic interconnection paths, the deposition of the final passivation and the masking for the opening of the accesses to the external electric systems.
Consequently, for manufacturing a pair of complementary transistors, i.e. a CMOS device, according to the current process described above, ten masking steps are required, i.e.: (1) definition and implantation of the zone with opposite doping with respect to that of the substrate; (2) definition of the active areas; (3) definition and implantation of the insulation regions on the substrate; (4) definition and implantation of the insulation regions in the zone; (5) definition of the gate electrodes and the interconnections in the polycrystalline silicon; (6) definition and implantation of the source and drain regions of the transistor in the substrate; (7) definition and implantation of the source and drain region of the transistor in the zone; (8) definition of the contacts; (9) definition of the metallic interconnection paths; (10) definition of the openings in the passivation layer.
It should be stressed, with reference to the foregoing, that the masking steps are indeed the most expensive steps of the process of manufacturing an integrated circuit, and the need is accordingly felt to reduce the number of required masking steps, in order to reduce the production cost of CMOS devices and bring it nearer to the cost of NMOS devices.